1. Field of the Invention
The present invention relates to a semiconductor memory device with repairing structure, and more particularly to a semiconductor memory device with redundancy structure in which a redundant memory cell therein is capable of being substituted for a defective memory cell therein.
2. Description of the Prior Art
As well-known in the art, a redundancy circuit has been used so as to prevent lowering in yield due to a defective memory cell occurring during fabrication of a high integrated semiconductor memory device. Such a redundancy circuit is provided in a normal memory cell array of the memory device. When a defect occurs in a memory cell, one of the redundant memory cells provided on the chip is substituted for the defective memory cell, thereby allowing the memory device to be normally operated. Substitution of a redundant memory cell for a defective memory cell is accomplished by the following method.
In detail, a row or column line corresponding to a defective memory cell is electrically or physically isolated from normal memory cells, and a redundant row line or a redundant column is electrically connected to a row decoder or a column decoder. The above substitution is generally performed directly before or after packaging a memory chip.
Column redundancy circuit is provided to substitute a redundant column for at least one of the defective columns corresponding to the defective memory cells, and has a redundant column selection circuit for disabling the defective columns and enabling redundant columns when the same column address as a programmed column address is applied. The programmed column address is set by a fusing circuit for programming a column address corresponding to the defective column.
Referring to FIG. 1, a conventional column redundancy circuit is broadly constituted by a redundant column selection circuit portion (hereinafter, referred to as "RCS circuit portion") 200 and a normal column selection circuit portion (hereinafter, referred to as "NCS circuit portion") 300. The RCS circuit portion 200 has a plurality of fusing boxes 2, 4, 6 for receiving column address signals CAa/ CAa, CAb/ CAb, . . . , CAn/ CAn, a plurality of inverter chains I1-I8, I1-I8, I1-I8 for delaying output signals FBO1, FBO2, . . . , FBON of the fusing boxes for a predetermined time, respectively, and producing redundant column selection signals RCS1, RCS2, . . . , RCSN, a plurality of NOR gates 8, . . . , 10 for receiving the output signals of the fusing boxes, NAND gate 12 for receiving all of the output signals of the NOR gates and an inverter 14 for generating a normal disable signal NCD by inverting the output signal of the NAND gate 12. The NCS circuit portion 300 has NAND gate 32 for receiving column address signal CAa, CAb, NAND gate 34 for receiving column address signal CAi, CAj, NAND gate 36 for receiving column address signal CAk, CAl, NAND gate 38 for receiving column address signal CAm, CAn, and a plurality of inverter chains I1-I5, I1-I5, I1-I5 for delaying output signals of the NAND gates 32, 34, 36, 38, respectively. Each of the fusing boxes serves as a programming means.
In FIG. 1, NAND gates 16 and 18, the NAND gates 32, 34, 36 and 38, and the plurality of inverter chains I1 through I5 constitute a column decoder. Column decoding signals DCAij, DCAkl and DCAmn are applied to the input of the NAND gate 18. The NAND gate 16 receives the normal disable signal NCD and the output signal (e.g. the signal of a node "A" shown in FIG. 1) of the inverter chain corresponding to the NAND gate 32, and generates a column decoding signal DCAab. Also, the circuit portion 300 further comprises p type MOS (hereinafter, referred to as "PMOS") transistor 20 having a gate terminal for receiving the column decoding signal DCAab, PMOS and n type MOS (hereinafter, referred to as "NMOS") transistors 22 and 24 each having a gate terminal for receiving the output signal of the NAND gate 18, PMOS transistor 26 having a gate terminal for receiving the column decoding signal DCAab and a drain terminal connected to an output node "B", inverter 28 for inverting the signal of the output node "B" and inverter 30 for inverting the output signal of the inverter 28 and producing a normal column selection signal NCS.
FIG. 2 illustrates the detailed construction of the fusing box shown in FIG. 1. In FIG. 2, the fusing box has an inverter 40, a plurality of NMOS transistors T1, T1', T2, T2', . . . , TN, TN', a plurality of fuses F1, F1', F2', . . . , FN, FN' capable of being switched, a plurality of NAND gates 48, . . . , 50 for receiving input signals responsive to each fusing state and producing an output signal, and NOR gate 52 for receiving output signals of the NAND gates and producing an output signal FBO of the fusing box. Each of the NMOS transistors has a gate terminal for commonly receiving a control signal RE, a first channel terminal for receiving a column address signal CAa, CAa, CAb, CAb, . . . , CAn, CAn, and a second channel terminal connected to one of the fuses. The fusing box further comprises a plurality of NMOS transistors 42, 44, 46 each having a gate terminal for receiving the output signal of the inverter 40, a drain terminal connected commonly to output terminals of the fuses F1 and F1', F2 and F2', . . . , FN and FN'. Each of the NMOS transistors 42, 44, 46 functions as a discharging transistor.
The fusing box of FIG. 2 is a circuit for programming a column address corresponding to a defective column. In FIG. 2, if the control signal RE is at the low level, all the NMOS transistors 42, 44, 46 are on and then a discharging operation occurs in each drain terminal thereof, thereby allowing the output signal FBO of the fusing box to be set to the low level. However, substitution of a redundant column for a defective column is accomplished by enabling the control signal RE to be the high level and electrically cutting a fuse connected to a column address input terminal not corresponding to a defective column address. After completion of the substitution, the defective column address corresponding to the defective column is applied to the input of the NAND gates 48, . . . , 50 and then is changed to the high level, thereby allowing the output signal FBO of the NOR gate 52 to be at the high level. Therefore, in the fusing box of FIG. 2, only when a defective column address is applied, the output signal FBO of the fusing box is set to be at the high level. This fusing box is usually called "NAND type fusing box". Programming of column address in the fusing box is accomplished by cutting (or fusing) a fuse connected to a column address input terminal not corresponding to a defective column address of the column address signals. It will be readily understood by those skilled in the art that, in the well-known NOR type fusing box different from the NAND type fusing box, programming of column address is accomplished by cutting a fuse connected to a column address input terminal corresponding to a defective column address. As shown in FIG. 1, because the RCS circuit portion 200 has a plurality of fusing boxes, e.g. a first fusing box 2, a second fusing box 4, . . . , an N-th fusing box 6, it can program defective column addresses corresponding to the N number of defective columns.
Hereinafter, operation of the normal and redundant column selection circuit portions is described in detail with reference to FIGS. 1 and 2.
First, in case that an external column address not corresponding to a defective column is applied, the column address signal CAa, CAa, CAb, CAb, . . . , CAn, and CAn applied to the RCS circuit portions 200 are compared with defective column address signals programmed in the fusing boxes. If two comparing signals are identical, all the fusing boxes 2, 4, . . . , 6 are set to generate the output signals FBO1, FBO2, . . . , FBON of low level. As a result, all of the redundant column selection signals RCS1, RCS2, . . . , RCSN are at the low level and thereby the redundant columns are not selected. Since the output signals FBO1, FBO2, . . . , FBON also are at the low level, output signals of the NOR gates 8, . . . , 10 are at the high level and thereby a normal column disable signal NCD of the high level is generated from the inverter 14. On the basis of the normal column disable signal NCD and a signal of the node "A" applied to input terminals of the NAND gate 16, a column decoding signal DCAab is generated from the NAND gate 16. The column decoding signals DCAij, DCAkl, DCAmn produced in responsive to the column address CAi, CAj, CAk, CAl, CAm, CAn are applied to three input terminals of the NAND gate 18. Therefore, the transistors 20, 22, 24, 26 are controlled in accordance with the column decoding signal DCAab and the output signal of the NAND gate 18 and thus the normal column selection signal NCS capable of selecting a normal column is generated.
On the other hand, when an external column address corresponding to a defective column is applied, the column address signals CAa, CAa, CAb, CAb, . . . , CAn, and CAn applied to the RCS circuit portions 200 are compared to defective column address signals programmed in the fusing boxes. If the external column address is identical to the defective column address programmed in one of the fusing boxes 2, 4, . . . , 6, for example the defective column address programmed in the first fusing boxes 2, the first fusing boxes 2 is enabled to generate the output signal FBO1 of the high level. As a result, the redundant column selection signal RCS1 is at the high level and thereby the redundant column can be substituted for the defective column. If the external column address is identical with defective address programmed in two fusing boxes, for example the first and second fusing boxes 2, 4, the first and second fusing boxes 2, 4 are enabled to generate the output signals FBO1, FBO2 of the high level. As a result, the redundant column selection signals RCS1, RCS2 are at the high level and thereby the redundant columns can be substituted for the defective columns. Also, the normal column disable signal NCD is at the low level and the normal column selection signal NCS also is at the low level.
As described above, in the column selection circuit portions 200 and 300 of FIG. 1, when an external defective column address corresponding to a defective column is applied, the first fusing box 2 is enabled to produce the output signal FBO1 of the high level and the normal column disable signal NCD is changed to the low level in response to the level of the output signal FBO1. Then, even if the node "A" is at the high level, the normal column selection signal NCS is at the low level owing to the low level of the normal column disable signal NCD and thereby the defective column is not selected.
The conventional column redundancy circuit of FIG. 1 has a structural feature that the normal column disable signal NCD for selecting a defective column is determined by the combination of signals FBO1, FBO2, . . . , FBON from the fusing boxes provided in the RCS circuit portion 200. In the case of this structural feature, since the normal column disable signal NCD is generated after passing through the NOR gate 8, . . . , 10, the NAND gate 12 and the inverter 14, the column redundancy circuit requires a gate passing time necessary for passing through the gates. Because of this gate passing time, there is a problem that, if the node "A" is maintained at the high level before the normal column disable signal NCD is changed to the low level, the conventional column redundancy circuit may be frequently real-operated due to a glitch occurring when the normal column selection signal NCS is maintained at the high level for a short time directly before setting the normal column disable signal NCD to the low level. Therefore, a first delay time a signal is passed through the input terminals of the fusing boxes to the node "A" has to be longer than a second delay time a signal is passed through the NAND and NOR gates 48, . . . , 50, 52 of the respective fusing box to the logic gates 8, . . . , 10, 12 and 14. When the first delay time is longer than the second delay time, the enabling time of the normal column selection signal NCS is dependent on the second delay time even if a defective column address is not applied. To shorten the enabling time of the signal NCS, it is necessary to reduce the number of the gates or shorten the delay lime passing through each gate.
As a semiconductor memory device becomes large in scale thereof and high in integration, the number of column address input terminals is increased in proportion. In the conventional column redundancy circuit of FIG. 1, however, it is difficult to reduce the number of gates provided in the fusing box in consideration of the appropriate number of the gates therein. Also, since the number of fusing boxes to be provided in the column redundancy circuit is increased in higher integration of a semiconductor memory device, it is difficult to reduce the number of gates provided between the output terminal of the fusing box and a terminal for producing the normal column disable signal NCS.